Assistant Professor, Electronics and Telecommuication Engineering
SSGMCE, Shegaon
swapnilbadar@mail.com
9503733768
Skills
HDL Coding (Verilog/VHDL)
VLSI Design - Circuit/Layout Level
Tools Handled
Cadence, Xilinx, Microwind, Multisim
Designed by me
8-bit polar decoder
32-bit Floating point multiplier
32-bit Fixed point Vedic multiplier
Operational Transconductace Amplifier
Radix - 2^4 Fast Fourier Transform
Languages
Marathi
English
Hindi
Research work in channel decoder for 5G technology
Rashtra Sant Tukdoji Maharaj Nagpur University, Nagpur
Sant Gadge Baba Amravati University, Amravati
Shri Sant Gajanan Maharaj College of Engineering , Shegaon
Bapurao Deshmukh College of Engineering, Sevagaram
Acharya Shiramannarayan Polytechnic, Pipri(Wardha)
One Week Online Workshop held at Shri Sant Gajanan Maharaj College of Engineering , Shegaon
Two Week Summer School held at Shri Sant Gajanan Maharaj College of Engineering , Shegaon
Two Days Workshop held at Shri Sant Gajanan Maharaj College of Engineering , Shegaon
Three Days Workshop held at Shri Sant Gajanan Maharaj College of Engineering , Shegaon
Four Week Summer School held at Shri Sant Gajanan Maharaj College of Engineering , Shegaon
Two Days Workshop held at Shri Sant Gajanan Maharaj College of Engineering , Shegaon
Two Days Workshop held at Shri Sant Gajanan Maharaj College of Engineering , Shegaon
For the paper "Implementation of Combinational Logic for Polar Decoder"at 2nd IEEE International Conference on Range Technology (ICORT-2021) during 5th -6th August 2021
Selected for "Training in Advanced Capabilities in Electronics Design and Manufacturing (TRIAC-EDM)" jointly orgnized by National Institute of Electronics & Information Technology, India and Institute for Information Industry, Taiwan
Completed two months "Summer Faculty Research Fellowship" of Indian Institute of Technology, Delhi during June-July 2020 under the guidance of Dr. Ankur Gupta
Certificate awarded for AICTE approved FDP of "Hardware modeling using Verilog" Aug-Oct 2019 (8 Week course) under NPTEL Online Certification
Runner for the project "Design and Development of Analog Circuits using Unconventional CMOS Techniques for Biomedical Applications" at national level Cadence Design Contest Bangalore in Jan 2019
1. S. P. Badar and K. Khanchandani, "Implementation of Combinational Logic for Polar Decoder" 2021 2nd International Conference on Range Technology (ICORT), 2021, pp. 1-6, doi: 10.1109/ICORT52730.2021.9581844.
2. S. Badar and D. R. Dandekar, "High speed FFT processor design using radix 2^4 pipelined architecture" 2015 International Conference on Industrial Instrumentation and Control (ICIC), 2015, pp. 1050-1055, doi: 10.1109/IIC.2015.7150901.
2. Network Analysis using Laplace Transform